Moore's Law may stop, or at least dramatically slow, around 2022 at the 7 nm CMOS node thanks to quantum effects and transistor threshold variability, according to Robert Colwell of DARPA.  At around 7 nm, electron tunnelling will make it difficult if not impossible to turn off today’s transistors.  In addition, the smaller number of atoms making up a transistor at 7 nm will require much more precise control of dopant atoms and transistor dimensions to maintain consistent transistor-to-transistor performance.

Today’s leading-edge for CMOS production at 22 nm will soon move to 14 nm and 10 nm assuming that the industry overcomes limitations to photolithography, which today combines liquid immersion with UV at 193 nm at the smaller nodes.  To reach 14 nm by 2015 in production devices, Intel is expected to extend today’s immersion lithography by going to deep UV with multiple masks.  Below 10 nm, e-beam lithography may be required, a more expensive, lower-throughput process than photolithography.

For denser memory ICs at smaller nodes, some have proposed memristors or spin-tronics.  Spin-torque oscillators in conventional CMOS could provide higher performance for RF circuits, which have just reached 28 nm for volume production with Qualcomm’s WTR3925L transceiver for cellphones.  At or below the 7 nm node, the semiconductor industry may have to give up conventional CMOS and silicon and switch to the TFET (tunnelling FET), which is thought to require direct bandgap semiconductors such as InGaAs / InP.  Some researchers have suggested moving to graphene (carbon-based) semiconductors.  Either would require retooling of present semiconductor fabs and many years for the industry to develop high-volume manufacturing experience and drive up yields for lower chip costs.

This gives us nine years until massive disuption of the electronics industry, and then around that time could give the GaAs & III-V suppliers a very big boost.